• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a circuit and a method for displaying a full white screen on a CRT screen when no signal is inputted from a computer main body and a vertical sync signal is not input. The circuit of the present invention includes a video preamplifier 22 and a video power amplifier 23 for receiving and amplifying an RGB video signal through a desub connector 21, and an RGB image output from the video power amplifier 23. A CRT 24 displaying a signal and a horizontal / vertical synchronous signal (H / V sync) are received through the de-sub connector 21 and supplied to the deflection unit 28 and connected to the de-sub connector 21. A microcomputer 26 for detecting a state, and a horizontal frequency (H.sync) and a vertical frequency (V.sync) set by receiving a control signal output from the microcomputer 26 when no signal is input to the deflection unit 28. A voltage drop is applied to the synchronous signal generator 27 to supply and the signals output from the first port P21 to the third port P23 of the microcomputer 26 to the video preamplifier 22 when no signal is applied. Impedance matching section 25 is configured. The present invention described above has the effect of displaying a full white pattern or a color-bar pattern as necessary without using an OSD-causing OSD IC.
    公开号:KR19990032800A
    申请号:KR1019970053952
    申请日:1997-10-21
    公开日:1999-05-15
    发明作者:임재섭
    申请人:전주범；대우전자 주식회사；
    IPC主号:
    专利说明:

    Circuit and method for making test pattern in a monitor
    The present invention relates to a method of displaying a full white screen on a CRT screen when no signal is inputted from a computer main body, and a vertical sync signal is not inputted.
    In general, a monitor is provided with an on-screen display integrated circuit for displaying text or graphic information on a CRT screen under the control of a microcomputer. The video system of the monitor with the OSD IC is illustrated in FIG. 1.
    Referring to FIG. 1, the SDA signal line and the SCL signal line are pulled up to 5V through the resistors R1 and R2, respectively, and are connected to the reset circuit through the capacitor C1 to power on the microcomputer 10 or the OSD IC. 11) are to be reset respectively.
    Meanwhile, the R, G, and B video signals output from the main body of the computer are input to the video preamplifier 12 through the de-sub connector, amplified to a predetermined level, and input to the mixer unit 13. The mixer unit 13 ), The R, G, B image signals and the OSD signals R ', G', B 'output from the OSD IC 11 are mixed, and the R, G, B images mixed by the mixer 13 are mixed. The signal and the OSD signals R ', G', and B 'are amplified again in the video power amplifier 14 and displayed on the CRT 15.
    As shown in FIG. 1, an I 2 C bus is widely used for transmitting control data between the microcomputer 10 and the OSD IC 11. The I 2 C bus is an SDA bus through which data is transmitted as a serial synchronization bus. And SCL buses, which carry synchronous clock signals, are the industry standard buses proposed by Philips to transmit data according to a predetermined protocol. For example, a bus signal line connected between a microcomputer and an OSD IC includes an SDA bus and an SCL signal line, and a reset signal line for resetting an integrated circuit.
    Typically, on an I 2 C bus, the SDA bus and SCL bus are pulled up in a "high" state and the data on the SDA bus is supposed to change only while the SCL bus is in a "low" period, where the SCL bus is in a "high" period. The transition of data from the SDA bus from "high" to "low" indicates "start" of the data transfer cycle, and the transition from "low" to "high" means the "stop" of the data transfer cycle. ".
    In addition, data or addresses are transmitted in units of 8-bit words on the I 2 C bus. A receiver receiving an 8-bit word drops the SDA bus to "low" at the ninth clock of the SCL bus to "ACKNOWLEDGE". Is displayed.
    Based on this basic protocol, the write operation and the read operation are performed. In general, the device address, word address, and data are sequentially transmitted in 8-bit units following "START", and finally, the end of transmission is notified by "STOP". At this time, the LSB "0" bit of the device address indicates a read / write operation. If "high", the bit indicates a read operation from the corresponding device. If the bit is "low", it indicates a write operation to the corresponding device. An ACK signal is sent each time a data or address is received.
    The microcomputer drives the OSD IC so that a full white screen is displayed on the CRT screen when a mode is switched in a non-signal mode or a multi-mode monitor in which a normal horizontal sync signal and a vertical sync signal are not input from the computer main body. This is to prevent this because the user suddenly darkens the screen and perceives it as a malfunction of the monitor or PC.
    However, as described above, many errors occur during data transfer between the microcomputer and the on-screen display integrated circuit through the I 2 C bus, and the OSD IC may be pulled up or pulled down due to static electricity or noise. If an error occurs as described above, there is a problem in that the power of the monitor must be turned off and then on again to reset the OSD IC.
    In addition, since the OSD IC is applied to an expensive monitor, that is, a large monitor, it is required for a circuit and a method for generating a test pattern such as a full white pattern or a color bar even in a monitor without an OSD IC. .
    Accordingly, the present invention has been made to meet the above necessity, and when a horizontal sync signal and a vertical sync signal are not input in a monitor without an on-screen display integrated circuit, a full white pattern is applied to a CRT screen. Its purpose is to provide a circuit and a method for generating the same.
    In order to achieve the above object, the circuit of the present invention is a monitor for receiving and amplifying an RGB image signal through a sub connector, and then displaying the signal on a CRT screen, wherein the horizontal / vertical synchronization signal is input through the sub connector. A micom that receives the deflector and detects a connection state with the de-sub connector, and a synchronous signal generator that receives a control signal output from the micom and supplies a horizontal frequency and a vertical frequency to the deflector when no signal is input; It characterized in that it is composed of an impedance matching section for supplying a video preamplifier by dropping the voltage output from the first port to the third port of the microcomputer when no signal.
    In addition, the circuit of the present invention includes the steps of: (a) entering a no-signal state in which the RGB image signal and the horizontal / vertical synchronization signal are not input; (b) detecting whether the de-sub connector is connected; (D) detecting whether there is a test pattern request key input if the sub-connector is connected in step (b); and (d) if there is a test pattern request key input in step (c), the color-bar pattern on the CRT screen. And (e) displaying the full white pattern on the CRT screen if the sub-connector is not connected in the step (b).
    1 is a block diagram showing a video system of a monitor to which a conventional microcomputer and on-screen display integrated circuit is applied,
    2 is a block diagram showing a test pattern generation circuit according to the present invention;
    3 is a flowchart illustrating a test pattern generation method according to the present invention;
    4 is a timing diagram illustrating a signal output by the microcomputer to display a color-bar pattern.
    * Explanation of symbols for main parts of the drawings
    21: Dedicated connector 22: Video preamp
    23: Video power amplifier 24: CRT
    25: impedance matching unit 26: micom
    27: synchronization signal generator 28: deflection unit
    Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
    FIG. 2 is a circuit diagram showing a test pattern generating circuit according to the present invention, FIG. 3 is a flowchart showing a test pattern generating method according to the present invention, and FIG. 4 is a first port through a first to display a color-bar pattern. A timing chart showing signals output from three ports.
    Referring to FIG. 2, the test pattern generating circuit according to the present invention includes a video preamplifier 22 and a video power amplifier 23 for receiving and amplifying an RGB image signal through a desub connector 21, and the video power amplifier. CRT (24) for displaying the RGB image signal output from the (23) and the horizontal / vertical synchronous signal (H / V sync) via the desub connector 21 is supplied to the deflection unit 28 and the A microcomputer 26 for detecting a connection state with the de-sub connector 21 and a horizontal signal (H.sync) and a vertical frequency (V.sync) set by receiving a control signal output from the microcomputer 26 when there is no signal. To the deflection unit 28 and the signal output from the first port (P21) to the third port (P23) of the microcomputer 26 and the video signal by dropping the voltage when no signal; The impedance matching unit 25 is supplied to the preamplifier 22.
    Here, the power terminal (Vcc) is connected to the ground terminal (⑥) of the sub connector 21 connected to the microcomputer 26 through the resistor R1, and thus the desub connector 21 is connected. In the state in which the low level signal is applied to the microcomputer 26 and the desub connector 21 is not connected, the high level signal is applied to the microcomputer 26.
    Referring to the operation and effects of the present invention configured as described above with reference to the flow chart of FIG.
    The absence of the horizontal / vertical sync signal (H / V sync) and the RGB video signal input to the monitor through the sub-connector 21 is called a no-signal state, which means that the de-connector 21 is connected to a computer. There is no signal output from the main body, and the case where the sub-connector 21 is not connected to receive a signal output from the computer main body can be divided into.
    In step 31, the microcomputer 26 detects whether there is a horizontal / vertical sync signal (H / V sync) input through the de-sub connector 21, and thus the horizontal / vertical sync signal (H / V sync) is not input. If no, go to Step 32.
    In step 32, the microcomputer 26 detects a state of a port connected to the ground terminal ⑥ of the deserve connector 21 and detects whether the deserve connector 21 is connected. If the level is 'low' level since the de-connector 21 is not connected, proceed to step 34, if the port is 'low' level, the de-sub connector 21 is connected, so proceed to step 33.
    In step 33, the user detects whether the user inputs a test pattern request key. In the no-signal state, since the H / V sync and RGB image signals are not input, the CRT screen becomes dark. A user who is embarrassed to see can press a separately prepared key to request that the test pattern be displayed.
    If there is a test pattern request key input in step 33, the process proceeds to step 35. In step 35, the microcomputer 26 displays the color-bar pattern on the screen of the CRT 24. That is, the micom 26 sequentially outputs a 'high' level pulse signal to the first port P21 to the third port P23 as shown in FIG. 4, wherein the pulse signal has a horizontal frequency. Repeated in cycles.
    Here, when the first port P21 is output at the 'high' level, the R image signal having a high level is input to the video preamplifier 22 through the impedance matching unit 25, so that the CRT screen 24 is red. When the bar is displayed and the second port P22 is output at the 'high' level, a G-level signal having a high level is input to the video preamplifier 22 to display a green bar, and the third port P23 is' During the high level, a blue bar is displayed on the screen of the CRT 24.
    At this time, the impedance matching unit 25 drops the 5V PP signal output from the first port (P21) to the third port (P23) of the microcomputer 26 to a signal of 0.7V PP video preamplifier 22 The video preamplifier 22 amplifies the 0.7V PP signal with an AC gain of about 4V to about 10V, and the video power amplifier 23 can drive the cathode of the CRT 24. Amplify to a signal of approximately 30V to 50V so that.
    If the sub connector 21 is not connected in step 32, the microcomputer 26 proceeds to step 34 and displays a full white pattern on the screen of the CRT 24. P21) to the third port P23 to output a 'high' level signal.
    That is, the signal output from the microcomputer 26 is dropped by the impedance matching unit 25 and applied to the video preamplifier 22. The signal is amplified by the video preamplifier 22 and the video power amplifier 23. After that the CRT screen is displayed.
    As described above, the microcomputer 26 displays the full white pattern in the non-signal state in which the sub-connector 21 is not connected, and displays the color-bar pattern in the non-signal state in which the de-connector 21 is connected. Display can provide psychological stability to users.
    As described above, the present invention has an effect of displaying a full white pattern or a color-bar pattern as needed without using an OSD IC that causes a lot of failures.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] In the monitor to receive and amplify the RGB video signal through the sub-connector to display on the CRT screen,
    A microcomputer that receives a horizontal / vertical synchronous signal through the desub connector and supplies it to a deflection unit, and detects a connection state with the desub connector;
    A synchronization signal generator for receiving a control signal output from the microcomputer and providing a set horizontal frequency and vertical frequency to the deflection unit when there is no signal;
    The test pattern generating circuit according to claim 1, wherein the test pattern generating circuit comprises an impedance matching unit for supplying the signal output from the first port to the third port of the microcomputer to a video preamp when the signal is no signal.
    [2" claim-type="Currently amended] (A) a step in which no RGB video signal and a horizontal / vertical synchronization signal are inputted;
    (B) detecting whether the disconnected connector is connected;
    (C) detecting whether there is a test pattern request key input if the sub-connector is connected in step (b);
    (D) displaying a color-bar pattern on the CRT screen if there is a test pattern request key input in step (c);
    And (e) displaying a full white pattern on the CRT screen if the sub-connector is not connected in step (b).
    [3" claim-type="Currently amended] 3. The method of claim 2, wherein step (d) is to sequentially output signals of a 'high' level through the first to third ports, and the step (e) may include the first to third ports. Test pattern generation method for a monitor, characterized in that the step of outputting a signal of the 'high' level at the same time.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-21|Application filed by 전주범, 대우전자 주식회사
    1997-10-21|Priority to KR1019970053952A
    1999-05-15|Publication of KR19990032800A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970053952A|KR19990032800A|1997-10-21|1997-10-21|Test pattern generating circuit and method in monitor|
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